Generally, at startup or reset of a transmitter, such as a transmitter used in a serializer-deserializer (“SERDES”), a buffer bypass mode was used. This buffer bypass mode was used to avoid skew introduced by a buffer of a transmitter for example. As data may be serialized over multiple lanes, multiple transmitters may introduce lane-to-lane skew by parallel use of their respective buffers, such as first-in, first-out buffers (“FIFOs”). However, a buffer bypass mode has significant circuitry overhead, among other limitations.
Furthermore, a clock network, such as an H clock tree or other clock network, may be used to provide a write clock to FIFOs corresponding to multiple transmitters. A clock network may have significant variance with such temperature variation. To compensate for such variation, a delay aligner may be used to adjustably drive a write clock into such clock network. A delay aligner may be a complex analog circuit, and use of a delay aligner may thus add to circuitry overhead of a buffer bypass mode of operation. Additionally, phase variation between write and read clocks may cut into timing margin, and as integrated circuits become more dense and larger, circuit may be more susceptible to differences in signal propagation delay, namely more susceptible to lane-to-lane skew.
Hence, it is desirable to provide skew equalization among multiple transmitters without one or more of the above-described limitations.